Conference Proceeding (25)

• 1:

  Title: Chen F; Ilatikhameneh H; Tan Y; Valencia D; Klimeck G; Rahman R, 2017, 'Transport in vertically stacked hetero-structures from 2D materials', in Journal of Physics: Conference Series
     

  Year : 2017

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  In this work, the transport of tunnel field-effect transistor (TFET) based on vertically stacked hereto-structures from 2D transition metal dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. WTe2-MoS2 combination was chosen due to the formation of a broken gap hetero-junction which is desirable for TFETs. There are two assumptions behind the MoS2-WTe2 hetero-junction tight binding (TB) model: 1) lattice registry. 2) The S − Te parameters being the average of the S − S and Te − Te parameters of bilayer MoS2 and WTe2. The computed TB bandstructure of the hetero-junction agrees well with the bandstructure obtained from density functional theory (DFT) in the energy range of interest for transport. NEGF (Non-Equilibrium Green's Function) equations within the tight binding description is then utilized for device transfer characteristic calculation. Results show 1) energy filtering is the switching mechanism; 2) the length of the extension region is critical for device to turn off; 3) MoS2-WTe2 interlayer TFET can achieve a large on-current of 1000µA/µm with VDD = 0.3V, which suggests interlayer TFET can solve the low ON current problem of TFETs and can be a promising candidate for low power applications.

  View
• 2:

  Title: Fay P; Li W; Digiovanni D; Cao L; Ilatikhameneh H; Chen F; Ameen T; Rahman R; Klimeck G; Lund C; Keller S; Islam SM; Chaney A; Cho Y; Jena D, 2017, 'III-N heterostructure devices for low-power logic', in China Semiconductor Technology International Conference 2017, CSTIC 2017
     

  Year : 2017

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  Future generations of ultra-scaled logic may require alternative device technologies to transcend the limitations of Si CMOS; in particular, power dissipation constraints in aggressively-scaled, highly-integrated systems make device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade especially attractive. Tunneling field effect transistors (TFETs) are one such device technology alternative. While a great deal of research into TFETs based on Si, Ge, and narrow band gap III-Vs has been reported, these approaches each face significant challenges. An alternative approach based on the use of III-N wide band gap semiconductors in conjunction with polarization engineering offers potential advantages in terms of drain current density and switching slope. In this talk, the prospects for III-N based TFETs for logic will be discussed, including both simulation projections as well as experimental progress.

  View
• 3:

  Title: Weber B; Hsueh YL; Watson TF; Li R; Hamilton AR; Hollenberg LCL; Rahman R; Simmons MY, 2017, 'Electron spin relaxation of single phosphorus donors and donor clusters in atomically engineered silicon devices', in 2017 Silicon Nanoelectronics Workshop, SNW 2017, pp. 23 - 24
     

  Year : 2017

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  We demonstrate the single-shot spin read-out of single donors and few-donor clusters, positioned with atomic precision by scanning tunneling microscopy (STM) in atomically engineered silicon devices [1-3]. In donor clusters, we measure spin lifetimes of up to half a minute, recorded at a read-out fidelity of up to 99.8% [2]. Importantly, measuring spin relaxations rates of electrons bound to a single P donor in orientation-dependent electric and magnetic fields, we identify a previously unreported spin relaxation pathway for donor-based qubits in silicon [1].

  View
• 4:

  Title: Nishat MRK; Tankasala A; Kharche N; Rahman R; Ahmed SS, 2017, 'Multiscale-multiphysics modeling of nonpolar InGaN LEDs', in 2017 IEEE 17th International Conference on Nanotechnology, NANO 2017, pp. 85 - 88
     

  Year : 2017

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  In this work, we develop and employ a multiscale-multiphysics simulator (based on coupled VFF molecular mechanics, 10-band sp 3 s*-spin tight-binding formalism, many-body full configuration interaction, and a TCAD transport module) to study and compare the performance of realistically-sized multiple-quantum-well wurtzite InGaN LEDs in polar (c-plane) and nonpolar (a-plane) crystallographic directions. The a-plane device exhibited smaller yet non-vanishing internal fields and higher optical transition rate as compared to the c-plane counterpart.

  View
• 5:

  Title: Long P; Povolotskyi M; Huang JZ; Ilatikhameneh H; Ameen T; Rahman R; Kubis T; Klimeck G; Rodwell MJW, 2016, 'Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors', in Device Research Conference - Conference Digest, DRC
     

  Year : 2016

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  Future VLSI devices will require low CV dd 2 /2 switching energy, large on-currents (I on ), and small off-currents (I off ). Low switching energy requires a low supply voltage V dd , yet reducing V dd typically increases /off and reduces the I on /I off ratio. Though tunnel FETs (TFETs) have steep subthreshold swings and can operate at a low V dd , yet their I on is limited by low tunneling probability. Even with a GaSb/InAs heterojunction (HJ), given a 2nm-thick-channel (001)-confined TFET, [100] transport, and assuming V dd =0.3V and I oFF =10 -3 A/m, the peak tunneling probability is <;3 % (fig. 1 a) and I on is only 24 A/m (fig. 1b) [1]. This low I on will result in large CV dd /I delay and slow logic operation. Techniques to increase /on include graded AlSb/AlGaSb source HJs [2,3] and tunneling resonant states [4]. We had previously shown that tunneling probability is increased using (11 0) confinement and channel heterojunctions [1], the latter increasing the junction built-in potential and junction field, hence reducing the tunneling distance. Here we propose a triple heterojunction TFET combining these techniques. The triple-HJ design further thins the tunnel barrier to 1.2 nm, and creates two closely aligned resonant states 57meV apart. The tunneling probability is very high, >50% over a 120meV range, and the ballistic I on is extremely high, 800A/m at 30nm Lg and 475 A/m at 15nm Lg, both with I off =10 -3 A/m and V dd =0.3 V. Compared to a (001) GaSb/InAs TFET, the triple-HJ design increases the ballistic /on by 26:1 at 30nm L g and 19:1 at 15nm L g . The designs may, however, suffer from increased phonon-assisted tunneling.

  View
• 6:

  Title: Huang JZ; Long P; Ilatikhameneh H; Ameen T; Rahman R; Povolotskyi M; Rodwell MJW; Klimeck G, 2016, 'Multiscale Transport Simulation of Nanoelectronic Devices with NEMO5', in 2016 PROGRESS IN ELECTROMAGNETICS RESEARCH SYMPOSIUM (PIERS), IEEE, Shanghai, PEOPLES R CHINA, pp. 914 - 914, presented at Progress in Electromagnetic Research Symposium (PIERS), Shanghai, PEOPLES R CHINA, 08 August 2016 - 11 August 2016
     

  Year : 2016

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  View
• 7:

  Title: Fay P; Li W; Cao L; Pourang K; Islam SM; Lund C; Saima S; Ilatikhameneh H; Amin T; Huang J; Rahman R; Jena D; Keller S; Klimeck G, 2016, 'Novel III-N heterostructure devices for low-power logic and more', in 16th International Conference on Nanotechnology - IEEE NANO 2016, pp. 767 - 769
     

  Year : 2016

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  Future ultra-scaled logic and low-power systems require fundamental advances in semiconductor device technology. Due to power constraints, device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade are essential if scaling of conventional computational architectures is to continue. Likewise, ultra low power systems also benefit from devices capable of maintaining performance under low-voltage operation. Towards this end, tunneling field effect transistors (TFETs) are one promising alternative. While much work has been devoted to realizing TFETs in Si, Ge, and narrow-gap III-V materials, the use of III-N heterostructures and the exploitation of polarization engineering offers some unique opportunities. From physics-based simulations, performance of GaN/InGaN/GaN heterostructure TFETs appear capable of delivering average SS approaching 20 mV/decade over 4 decades of drain current, and on-current densities exceeding 100 μA/μm in aggressively scaled nanowire configurations. Experimental progress towards realizing III-N based TFETs includes demonstration of GaN/InGaN/GaN backward tunnel diodes by both MOCVD and MBE, and nanowires grown selectively by MBE and used as the basis for device fabrication.

  View
• 8:

  Title: Long P; Huang JZ; Povolotskyi M; Verreck D; Klimeck G; Rodwell MJW, 2016, 'High-current InP-based triple heterojunction tunnel transistors', in 2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS), IEEE, presented at 2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS)], 26 June 2016 - 30 June 2016
     

  Year : 2016

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  We report the design and simulated performance of a GaAsSb/GaSb/InAs/InP n-type triple heterojunction (3-HJ) tunnel field-effect transistor (TFET). GaAsSb/GaSb source and InAs/InP channel HJs both increase the field imposed upon the tunnel junctions and introduce two resonant bound states. The tunneling probability, and hence the transistor on-current, are thereby greatly increased. The devices were simulated using a non-equilibrium Green function quantum transport approach and the k.p method within NEMO5. With 10 -3 A/m (I OFF ) and a 0.3 V power supply V DD , we simulate 380 A/m ON-current (I ON ) at 30-nm gate length (L g ) and 275 A/m at 15-nm L g . Unlike a previously-reported high-current AlGaSb/GaSb/InAs/InGaAsSb 3-HJ design, the GaAsSb/GaSb/InAs/InP design employs channel materials to which high-quality, low-interface-state-density gate dielectrics have been demonstrated.

  View
• 9:

  Title: Weber B; Tan YHM; Mahapatra S; Watson TF; Ryu H; Lee S; Rahman R; Hollenberg LCL; Klimeck G; Simmons MY, 2015, 'Silicon at the fundamental scaling limit-atomic-scale donor-based quantum electronics', in 2014 Silicon Nanoelectronics Workshop, SNW 2014
     

  Year : 2015

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  On the route to scalability in donor-based quantum computing architectures, we report on recent advances in the atomic-precision engineering of donor-based electronic devices in silicon, fabricated by STM hydrogen lithography, gas-phase δ-doping, and silicon homoepitaxy [1-3].

  View
• 10:

  Title: Mohiyaddin FA; Rahman R; Kalra R; Lee S; Klimeck G; Hollenberg LCL; Yang CH; Rossi A; Dzurak AS; Morello A, 2015, 'Designing a large scale quantum computer with atomistic simulations', in 2014 Silicon Nanoelectronics Workshop, SNW 2014
     

  Year : 2015

  Publication Type: Conference Proceeding

  Topic:

  Abstract

  We present atomistic modeling and design of nanostructures, required to demonstrate the essential ingredients-spin readout, control, exchange and transport-of a spin based quantum computer in silicon.

  View